Synaptic 1/f noise injection for overfitting suppression in hardware neural networks

Adaptive Thresholds for Neural Networks with Synaptic Noise

The inclusion of a macroscopic adaptive threshold is studied for the retrieval dynamics of both layered feedforward and fully connected neural network models with synaptic noise. These two types of architectures require a different method to be solved numerically. In both cases it is shown that, if the threshold is chosen appropriately as a function of the cross-talk noise and of the activity o...

Adaptive Thresholds for Layered Neural Networks with Synaptic Noise

The inclusion of a macroscopic adaptive threshold is studied for the retrieval dynamics of layered feedforward neural network models with synaptic noise. It is shown that if the threshold is chosen appropriately as a function of the cross-talk noise and of the activity of the stored patterns, adapting itself automatically in the course of the recall process, an autonomous functioning of the net...

On-off intermittency in small neural networks with synaptic noise

Fast Prototyping for Hardware Neural Networks

Neural algorithms and architectures are rarely tested on actual hardware testbeds owing to the high cost and long time required to develop neural chips. A Fast Prototyping Neural System FPNS where neural architectures can be easily programmed and conngured on programmable chips is here presented. Two diierent case studies were developed and used as benchmark for our system, showing a good perfo...

A Hardware Emulator for Binary Neural Networks

A neural network emulator is described in this paper. The device can implement neural networks of various architectures, provided that the inputs and outputs of neurons are binary. The device is fully digital. It is mainly composed of 128 serial adders, and can be viewed as a 128-processor specialized SIMD machine. It can emulate neural layers of any size, only depending on the amount of RAM at...